1. Field of the Invention
The present invention relates to a wafer test circuit for a semiconductor memory device and, more particularly, to a wafer burn-in test circuit and a method of testing a semiconductor memory device which tests for defects in the semiconductor device by applying a stress voltage which exceeds the normal operating voltage of the device.
2. Description of the Related Art
Manufacturers of semiconductor memory devices usually perform a burn-in test to test for memory cell defects after manufacturing is substantially complete. The burn-in test is typically performed after the chip is packaged. Therefore, if it is determined in the final burn-in test step that there is a defect in the wafer, the failed portion of the wafer is discarded, even though the manufacture of the product is substantially complete. The test method is therefore inefficient.
It would be desirable to perform the wafer burn-in test earlier in the manufacturing process. A scheme is exemplified to perform the burn-in test in the wafer fabrication step. Specifically, in case of a dynamic random access memory (DRAM), most of burn-in failures are the single bit failure, the testing for which requires much time. A single bit failure is directly related to a leakage of an incomplete memory cell. The current leakage results from defects in the transmission gate oxide, capacitor dielectric and memory node junction. A conventional wafer burn-in (WBI) testing circuit is realized differently depending upon the word line structure of the memory device. In addition, each node stress is also variable according to the WBI operation. Exact screening is therefore not possible.
FIG. 1 illustrates a WBI structure applicable to a memory cell array structure of a subword-line driver.
A row decoder (not shown) provides decoded addresses .psi.PRE1 and .psi.PRE2 to the subword-line driver of FIG. 1 in a normal operating mode to thereby drive a word line WL and thus select an intended cell. The word line driver is made up of transistors 101 through 103, inverter 104 and transistors 105, 106. The operation of the subword-line driver of FIG. 1 is described first during normal operation and then during a wafer burn-in test performed by the manufacturer.
A wafer burn-in enable signal WBI is a low level signal during normal operation. A row predecoding signal .psi.PRE1 is also low. A low predecoding signal/.psi.PRE2 is an inverted signal of the predecoding signal .psi.PRE2. To place the circuit in the wafer burn-in test mode, the wafer burn-in enable signal WBI is set to a high level thereby turning on the transistor 105. A word line stress voltage Vstress is applied through the path for discharging the word line WL, so that the stress affects the memory cell. This kind of circuit operation screens for oxidation defects of the transmission transistor due to the word line stress, but cannot apply a bit line stress because all of the word lines are enabled and the same data is therefore written into the cell connected to the corresponding word line. The same voltage is therefore applied between the bit lines and defective cells, which might be affected by a large stress potential, are not destroyed and thus not detected during testing.